1. Field of the Invention
The present invention relates to electrically programmable and erasable non-volatile memory, and more particularly to charge trapping memory with limited charge storage states per charge trapping memory cell.
2. Description of Related Art
Electrically programmable and erasable non-volatile memory technologies based on charge storage structures known as flash memory are used in a variety of modem applications. As the dimensions of integrated circuits shrink, greater interest is arising for memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Memory cell structures based on charge trapping dielectric layers include structures known by the industry name PHINES, for example. These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As negative charge is trapped or positive charge is removed, the threshold voltage of the memory cell increases. Conversely, the threshold voltage of the memory cell is reduced by removing negative charge from the charge trapping layer or adding positive charge to the charge trapping layer.
Charge trapping memory cell structures such as PHINES take advantage of the localized charge storage nature of charge trapping, by storing multiple charge storage states. Unlike the floating gate structure, which is an essentially equipotential structure with material such as polysilicon, localized charge storage materials are not equipotential, and can store different amounts of charge in distinct portions of the same charge storage structure. Thus, a single charge trapping memory cell can store, for example, two distinct charge storage states—one physically located by the source of the memory cell, and another physically located by the drain of the memory cell.
However, the scalability of such PHINES structures may be more limited, because the multiple charge storage states of a single memory cell will interact with each other, despite being separated physically in the same charge storage structure. This interaction between multiple charge storage states of a single memory cell will worsen as the size of memory cells shrinks.
Although the PHINES structure with multiple charge storage states of a single memory cell is less scalable, the charge trapping structure of the memory cell with its localized charge storage nature remains advantageous, because less charge is required to program a particular memory cell. Unlike equipotential structures such as floating gates, programmed charge added to a charge trapping structure will not diffuse automatically throughout an entire charge storage structure, which allows changes in the charge storage state of a charge trapping structure to be effected with less total charge.
Thus, a need exists for a nonvolatile memory cell which takes advantage of the localized charge storage nature of charge trapping memory cells, without suffering the scalability issues resulting from storing multiple charge storage states in a single nonvolatile memory cell.